Currently, electronic appliances using semiconductor devices, such as semiconductor chips, are highly sophisticated. In addition, high density mounting of the semiconductor chips onto a substrate, downsizing of the substrate on which the semiconductor chips are mounted, and a smaller footprint of the substrate are being required.
In view of the above, a substrate in which the semiconductor chips are embedded, or a so-called chip embedded substrate, and various configurations for embedding the semiconductor chips in the substrate have been proposed. Additionally, along with progress in miniaturization of electric lines of the semiconductor chips, the wiring of the chip embedded substrate is also required to be miniaturized and multilayered.
However, as the wiring structure of the chip embedded substrate becomes miniaturized and multilayered, it takes a longer time to produce the chip embedded substrate, which may bring about a disadvantage of lower production efficiency. In addition, the miniaturized and multilayered wiring structure may cause lower production yields. Especially, since expensive semiconductor chips are embedded in the chip embedded substrate, lower production yields of the chip embedded substrates may lead to a waste of many, expensive semiconductor chips.
Patent-related document 1 (Japanese Patent Application Laid-Open Publication No. 2003-347722) discloses a method of stacking substrates on which semiconductor chips are mounted. However, the invention disclosed by this document merely relates to a method of stacking substrates. The document does not disclose or suggest any measures to address the lower production yields caused when the wiring structure of the chip embedded substrate is miniaturized and multilayered.
[Patent-related document 1] Japanese Patent Application Laid-Open Publication No. 2003-347722